Boolean mask operations on parameterized 45-degree polygons

Since analog circuits are usually very sensitive, it is desirable to consider layout-induced parasitic effects early in a design flow. In a proposed layout-aware analog design methodology based on the use of parameterized 45-degree layouts, parasitics can be estimated in the circuit synthesis phase if models of extracted circuits can be generated from these layouts. In order to perform circuit extraction from parameterized 45-degree layouts, algorithms are required for dealing with parameterized 45-degree polygons and relevant constraints. In particular, algorithms for performing Boolean mask operations on parameterized 45-degree polygons are essential in the circuit extraction process. In this paper, an efficient approach is proposed for performing Boolean mask operations on parameterized 45-degree polygons. To the best of our knowledge, this paper is the first in the literature to present an approach for performing these operations.