Modeling of transient faults and fault-tolerant design in nanoelectronics

Transistors in nanometric technologies are increasingly susceptible to faults due to physical limitations. Since the constituent gates of a logic circuit actually have different failure rates, the assumption of constant gate failure rate in existing reliability evaluation and fault tolerant design is not desirable. This paper analyzes transient faults in CMOS logic gates at transistor level and proposes a mathematical model. Examples based on the benchmark circuit are provided to demonstrate the efficiency of the proposed model in both reliability evaluation and fault tolerant design.