• DocumentCode
    649314
  • Title

    Accuracy and speed limitations in DACs across CMOS process technologies

  • Author

    Yoder, Samantha M. ; Balasubramanian, S. ; Khalil, Waleed ; Patel, Vipul J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA
  • fYear
    2013
  • fDate
    4-7 Aug. 2013
  • Firstpage
    868
  • Lastpage
    871
  • Abstract
    We present a study of accuracy and timing limitations in current-steering digital-to-analog converters (DACs). Effects of limited output impedance and device mismatches on the DAC performance are discussed and observed for a 10-bit DAC operating at 4 GS/s. These limitations are also studied across 180, 90, and 65 nm CMOS process technologies.
  • Keywords
    CMOS integrated circuits; digital-analogue conversion; electric impedance; CMOS process technologies; DAC performance; bit rate 4 Gbit/s; current-steering digital-to-analog converters; device mismatches; output impedance; size 180 nm; size 65 nm; size 90 nm; speed limitations; timing limitations; word length 10 bit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
  • Conference_Location
    Columbus, OH
  • ISSN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2013.6674787
  • Filename
    6674787
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=649314