• DocumentCode
    649351
  • Title

    Digital Down Converter optimization

  • Author

    Gerhardt, Joe ; Ren, Shaolei

  • Author_Institution
    Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
  • fYear
    2013
  • fDate
    4-7 Aug. 2013
  • Firstpage
    1015
  • Lastpage
    1018
  • Abstract
    A Digital Down Converter (DDC) using four times intermediate frequency (4fIF) sampling is analyzed to simplify the required hardware. The DDC is controlled by a two bit counter. One counter bit controls the mixer, implemented as a two input multiplexer, while the other bit controls data flow in direct or transposed form finite impulse response (FIR) filters. The resulting FIR filters significantly reduce the number of multipliers and adders required while still allowing additional filter reduction techniques to be applied.
  • Keywords
    FIR filters; adders; convertors; 4fIF sampling; DDC; FIR filter; adder; digital down converter optimization; filter reduction technique; finite impulse response; four times intermediate frequency; multiplexer; multiplier; two bit counter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
  • Conference_Location
    Columbus, OH
  • ISSN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2013.6674824
  • Filename
    6674824
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=649351