DocumentCode :
649354
Title :
A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance
Author :
June-Hee Lee ; Sang-Hoon Kim ; Jong-Shin Shin ; Dong-Chul Choi ; Kee-Won Kwon ; Jung-Hoon Chun
Author_Institution :
Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
1027
Lastpage :
1030
Abstract :
A new technique to achieve high jitter tolerance and fast frequency acquisition with low logic latency for MIPI Low Latency Interface (MIPI LLI) applications is proposed. The proposed tracked oversampling CDR increases the allowable phase difference between the recovered and embedded reference clock up to 1.25 UI. The CDR loop gain can be adjusted based on the digitally estimated phase difference, resulting in short acquisition time (≤ 1 baud period) and high jitter tolerance (167-UIp-p 100-kHz jitter). Utilizing a bit selector with an edge tracking finite state machine (FSM) instead of an elastic FIFO, a logic latency less than 2 baud periods is achieved. The core circuit is implemented using a 65nm CMOS technology. It consumes 4.7mW from a 1.2V power supply at 5.8Gb/s.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; finite state machines; jitter; logic circuits; CDR loop gain; CMOS technology; FSM; MIPI LLI; MIPI low latency interface; bit rate 5.8 Gbit/s; bit selector; digital data recovery; edge tracking finite state machine; frequency 100 kHz; frequency acquisition; jitter tolerance; low logic latency; phase difference; power 4.7 mW; size 65 nm; tracked oversampling CDR; voltage 1.2 V;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674827
Filename :
6674827
Link To Document :
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