Phase-noise tuneable ring voltage-controlled oscillator in 90 nm CMOS

An architecture that compensates the sensitivity to process variation of the phase-noise performance of a ring voltage-controlled oscillator (VCO) is presented. The architecture consists of a VCO subdivided into 10, individually activated sub-VCOs whose outputs are connected together through pass-transistor switches. By varying the number of active sub-VCOs, per-die tuning of phase noise and power dissipation is enabled. Monte-Carlo simulations in ST 90 nm CMOS show a 36 % reduction in the worst case and 41 % reduction in the average power dissipation of a design required to satisfy the same phase-noise specification. Measured results show that phase noise can be traded-off against power dissipation on a per-die basis. The technique is also applicable to multi-rate wireline systems in which different data rates require different jitter specifications.