A 10-bit 64MS/s SAR ADC using variable clock period method

This paper presents a low-power 10-bit 64MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for Built-In Self Test (BIST) that uses a monotonic capacitor switching and variable clock period method for single input condition. To achieve high speed, a non-fixed clock time technique is used to reduce not only peak current but also die area. The technique removes conversion time waste and extends the SAR operation speed over 64MHz easily. Compared to the converters that use the conventional procedure, maximum peak current and DAC driver´s area are reduced by about 33.8% and 25.2%, respectively. Single input ADC generally limits the resolution unlike the differential input ADC. However, the proposed ADC in this paper achieves high resolution and accuracy with a single input signal. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. Using 1.2V supply and the sampling rate of 64 MS/s, the ADC achieves a SNDR of 50.2 dB and consumes 1.325 mW. The ADC core occupies an active area of only 185μm×210μm.