DocumentCode
649398
Title
Trusted verification test bench development for Phase-Locked Loop (PLL) hardware insertion
Author
Kimura, Adam G. ; Kai-Wei Liu ; Prabhu, Shashank ; Bibyk, Steven B. ; Creech, Gideon
Author_Institution
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA
fYear
2013
fDate
4-7 Aug. 2013
Firstpage
1208
Lastpage
1211
Abstract
Trusted design and verification presents new challenges for the case of using Intellectual Property (IP) in mixed signal systems. A Digitally Controlled Oscillator (DCO) subcomponent of a Phase-Locked Loop (PLL) is utilized as an example through which the presented verification principles may be applied to PLL tests on the Texas Instruments Analog System Lab Kit Pro (TI ASLK Pro). A VHDL model has also been developed, incorporating Assertion-Based Verification (ABV) as a means for trusted verification of the design.
Keywords
electronic engineering computing; formal verification; hardware description languages; industrial property; integrated circuit testing; oscillators; phase locked loops; ABV; DCO subcomponent; PLL hardware insertion; PLL tests; TI ASLK Pro; Texas Instruments Analog System Lab Kit Pro; VHDL model; assertion-based verification; digitally controlled oscillator subcomponent; intellectual property; mixed signal systems; phase-locked loop hardware insertion; trusted design; trusted verification test bench development;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location
Columbus, OH
ISSN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2013.6674871
Filename
6674871
Link To Document