A variable-latency floating-point division in association with predicted quotient and fixed remainder

A new algorithm to accelerate the execution of floating point division for the final quotient is presented in this paper. In this algorithm, the quotient of each step is predicted and then the final quotient is achieved by accumulating all the predicted quotients. If the prediction is correct, the number of iterations can be reduced and thus the speed increases. Generally, about 5 iterations are needed to reach a final quotient, but the number of this iteration could be bigger or smaller depending on the accuracy of the prediction, the capacity of the accumulated quotient, the comparison with the result register, the number of fractions and the required remainder set by users. In addition, the proposed method only takes up 0.4% to 6% area on a Field-Programmable-Gate-Arrays (FPGA) chip which is quite small. The study also shows that if there are more values in Look-Up-Table (LUT), the final quotient can be found faster with only fewer iterations. By extending more bits for quotient (the bit width of original quotient is 5-bits), we accelerated the procedure to achieve the final quotient and the needed number of additions is significantly reduced.