On-chip decoupling architecture with variable nMOS gate capacitance for security protection

This paper presents a new on-chip partial decoupling architecture with variable nMOS gate capacitance as a countermeasure against power analysis attacks. The preferred form of the countermeasure consists of a decoupling switch and primary gate capacitor along with a bank of secondary gate capacitors which are coupled and decoupled in a random fashion. This provides a means of decoupling a sensitive cryptographic module from the power supply with low overhead and low design complexity. The random use of the secondary decoupling gate capacitors serves to mix and hide indirectly leaked side channel information from previous charge/discharge cycles. An implementation of the proposed architecture protecting an AES Sbox module was implemented in 65 nm CMOS TSMC technology. Simulations were performed using Cadence. Initial results conducted using 2000 traces collected at the power supply pin of the design show that the proposed countermeasure protects against correlation power analysis attacks.