A family of modular area- and energy-efficient QRD-accelerator architectures

Author

Vishnoi, Upasna ; Noll, Tobias G.

Author_Institution

Electr. Eng. & Comput. Syst., RWTH Aachen Univ., Aachen, Germany

fYear

2013

fDate

23-24 Oct. 2013

Firstpage

1

Lastpage

8

Abstract

QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-level optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.

Keywords

CMOS integrated circuits; digital arithmetic; signal processing; CMOS; CORDIC rotations; Givens algorithm; QR decomposition accelerators; QRD architectures; SoC components; algebraic cost model; circuit level; cross level optimization; energy efficient QRD accelerator architectures; integer/floating point QRD; microarchitecture; modular area; template architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

System on Chip (SoC), 2013 International Symposium on

Conference_Location

Tampere

Type

conf

DOI

10.1109/ISSoC.2013.6675277

Filename

6675277