DocumentCode
64962
Title
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Author
Titos-Gil, Ruben ; Negi, Atul ; Acacio, M.E. ; Garcia, Juan Manuel ; Stenstrom, Per
Author_Institution
Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
Volume
24
Issue
11
fYear
2013
fDate
Nov. 2013
Firstpage
2192
Lastpage
2201
Abstract
Hardware transactional memory (HTM) designs are very sensitive to the manner in which speculative updates from transactions are handled in the system. This study highlights how the lack of effective techniques for store management results in a quick degradation in the performance of eager HTM systems with increasing contention and, thus, lends credence to the belief that eager designs do not perform as well as their lazy counterparts when conflicts abound. In this work, we present two simple ways to improve handling of speculative stores--a way to effectively manage lines that exhibit migratory sharing and a way to hide store latency, particularly for those stores that target contended cache lines owned by other concurrent transactions. These two mechanisms yield substantial improvements in execution time when running applications with high contention, allowing eager designs to exceed the performance of lazy ones. Interestingly, the benefits that accrue from these enhancements can be at par with those achieved using more complex system-wide HTM techniques. Coupled with the fact that eager designs are easier to integrate into cache coherent architectures than lazy ones, we claim that with judicious management of stores they represent a more compelling design alternative.
Keywords
parallel programming; storage management; cache coherent architectures; complex system-wide HTM techniques; contended cache lines; eager HTM systems; eager hardware transactional memory; latency storage; migratory sharing; parallel programming; store management; Buffer storage; Coherence; Concurrent computing; Hardware; Optimization; Parallel processing; Scalability; Parallel programming; multicore architectures; transactional memory;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/TPDS.2012.315
Filename
6342882
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