Title :
High-speed LDPC encoder architecture for digital video broadcasting systems
Author :
InKi Lee ; DeockGil Oh ; MinHyuk Kim ; Jiwon Jung
Author_Institution :
Satellite & Wireless Convergence Res. Dept., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Abstract :
In this paper, we propose a high-speed LDPC encoder architecture for the DVB-S2 standard. The proposed LDPC encoding architecture is based on parallel 360 bit-wise operations. The key issues for realizing a high speed are two kinds of index addresses and making efficient use of memory. We implemented a half-rate LDPC encoder on an FPGA, and confirmed that its maximum throughput is up to 10 Gbps with a 100 MHz clock.
Keywords :
clocks; digital video broadcasting; field programmable gate arrays; parity check codes; DVB-S2 standard; FPGA; clock; digital video broadcasting systems; frequency 100 MHz; half-rate LDPC encoder; high-speed LDPC encoder; index address; word length 360 bit; DVB-S2; LDPC encoder; Memory;
Conference_Titel :
ICT Convergence (ICTC), 2013 International Conference on
Conference_Location :
Jeju
DOI :
10.1109/ICTC.2013.6675433
