Title :
Comparison of performance of high speed VLSI adders
Author :
Jayanthi, A.N. ; Ravichandran, C.S.
Author_Institution :
Dept. of ECE, Sri Ramakrishna Inst. of Technol., Coimbatore, India
Abstract :
In modern VLSI design, the occurrence of delays is predictable. Many digital systems that process data may have delays. Design requires thorough understanding of algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this research work, 16-bit and 64 bit adder is designed and comparison is made between all types of adders in terms of delay. Xilinx ISE is used for simulation and synthesis Delay of 13.88 ns for a 16 bit Ling adder and 64 bit Sparse 2 adder has a delay of 35.026 ns. Area is also measured and comparison is made.
Keywords :
VLSI; adders; high-speed integrated circuits; logic design; Ling adder; Sparse 2 adder; VLSI design; Xilinx ISE; circuit design techniques; circuit sizing; digital systems; energy tradeoff; high speed VLSI adders; recurrence structures; system constraints; time 13.88 ns; time 36.026 ns; wire tradeoff; word length 16 bit; word length 64 bit; CLA Adder; Energy-Delay Optimization; High Speed Arithmetic; Low Power Design; RCA;
Conference_Titel :
Current Trends in Engineering and Technology (ICCTET), 2013 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2583-4
DOI :
10.1109/ICCTET.2013.6675920
