Low power and high speed AES using mix column transformation

It is crucial to design energy-efficient advanced encryption standard (AES) cryptography for low power embedded systems powered by limited battery. We will present the hardware architecture to implement low power AES crypto module. Our low power AES crypto module has optimized architecture of data encryption unit and key schedule unit which could be applicable to wireless sensor networks. We also details low power design methods used to design our low power AES crypto module. The power consumption and area is further decreased by inserting compact and flexible architecture for mix column transform. The proposed AES algorithm achieves a high speed and low area when compared with the existing methods.