DocumentCode :
649925
Title :
Design and analysis of nonlinear AES S-box and mix-column transformation with the pipelined architecture
Author :
Gopi, V. ; Logashanmugam, E.
Author_Institution :
St. Peter´s Univ., Chennai, India
fYear :
2013
fDate :
3-3 July 2013
Firstpage :
235
Lastpage :
238
Abstract :
Cryptography plays an important role in the security of data. It enables us to store sensitive information or transmit it across insecure networks so that unauthorized persons cannot read it[1]. In this paper, we use FPGA chips to realize high data throughput AES pipelined architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. In this paper we have detailed the alternative design of both direct, inverse Mix Column transforms and high secure nonlinear S-box required in the AES hardware implementation and apply the pipeline architecture for high speed application.
Keywords :
cryptography; AES hardware; AES modules; FPGA chips; cryptography; high data throughput AES pipelined architecture; insecure networks; inverse mix column transforms; mix column transformation; nonlinear AES S-box; pipeline architecture; security of data; sensitive information; AES; Architecture; Cryptography; Encryption; FPGA; Security processor; cipher; pipeline;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Current Trends in Engineering and Technology (ICCTET), 2013 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2583-4
Type :
conf
DOI :
10.1109/ICCTET.2013.6675955
Filename :
6675955
Link To Document :
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