Design of a highly linear fully integrated wideband LNA in 0.13µm CMOS technology

This work presents the design of a 2.1-3.1GHz wideband Low Noise Amplifier (LNA) in 0.13μm CMOS technology from IBM. A single ended cascode configuration with inductive degeneration is used. The circuit is designed in Cadence and employs feed forward distortion cancellation technique to improve linearity. The layout is designed in Virtuoso XL and post layout simulations are performed using Assura 1.8.0.1 DM. At 2.45GHz, the low noise amplifier has a gain of about 10.0dB, noise figure of 1.66dB, input referred P1dB of -4.78dBm, output referred P1dB of 5.22dBm, IIP3 of +11.1dBm and OIP3 of +21.77dBm consuming 8.48mA from 1.5V supply. This design has the best input referred P1dB and IIP3 reported till date in 0.13μm technology for the desired frequency of operation.