A 10Gbps in-line Network Security Processor with a 32-bit embedded CPU

This paper presents design and verification of a 10Gbps in-line Network Security Processor (NSP) with a single 32-bit embedded CPU. This NSP is designed to process the IPSec protocol at line speed for the 10Gbps Ethernet. 10Gbps SerDes, IPSec protocol processing module, database query module, and a CPU are designed to be integrated on one chip to form a System on Chip (SOC). The CPU used is OR1200, a 32-bit open source general-purpose CPU with Harvard Microarchitecture. The CPU acts as the controller, bringing flexibility and scalability to the system. Virtex-5 XC5VXS95T FPGA board is used in the verification.