An energy efficient inverter based readout circuit for capacitive sensor

This paper presents a high energy efficient, parasitic free and low complex readout integrated circuit for capacitive sensors. A very low power consumption is achieved by replacing a power hungry operation amplifier by a subthreshold inverter instead in a switched capacitor amplifier(SC-amp) and reducing the supply voltage of all digital circuits in the system. A fast respond finite gain compensation method is utilized to reduce the gain error of the SC-amp and increase the energy efficiency of the readout circuit. A two-step auto calibration is applied to eliminate the offset from nonideal effects of the SC-amp and comparator delay. The readout system is implemented and simulated in TSMC 90 nm CMOS technology. With supply voltage of 1 V, simulation shows that the circuit can achieve 10.4 bit resolution while consuming only 3 μW during 640 μs conversion time. The digital output code has little sensitivity to temperature variation.