Register Allocation by Incremental Graph Colouring for Clustered VLIW Processors

This paper presents an incremental register allocator based on graph colouring for clustered VLIW processor. This register allocator is integrated with an instruction scheduler which schedules all the basic blocks of a program in reverse postorder and all the operations of each basic block based on their priorities. When scheduling an operation, the register allocator assigns physical registers to virtual registers of the operation by incremental graph colouring. Our approach is an integrated approach which can avoid the traditional phase ordering problem. We have simulated our approach and a previous approach CARS using a set of benchmarks. The simulation results show that our approach outperforms CARS by 9.03%, 13.43%, 10.35% for three processor models, respectively, in terms of the average schedule lengths of basic blocks.