DocumentCode :
652341
Title :
Celerity Hardware Implementation of the AES with Data Parallel and Pipelining Architecture inside the Round Function
Author :
Shouwen Yang ; Hui Li ; Xiaotao Zhang ; Gang Zhao
Author_Institution :
Inf. Security & Intell. Comput. Lab., Beijing Univ. of Chem. Technol., Beijing, China
fYear :
2013
fDate :
16-18 July 2013
Firstpage :
1690
Lastpage :
1695
Abstract :
Since it was accepted as the replacement of the Data Encryption Standard (DES) and 3 DES by NIST in 2001, the AES has played a major role in various security-constrained applications. Many applications are power-saving, resource constrained and require high-speed. AES is precisely suitable for being implemented in both software and hardware applications. Hardware implementation of AES has the advantage of increased throughput and better security. On the basis of those facts, in this paper, different hardware architectures of AES have been presented and surveyed. And we present a way of data parallel to deal with the bulk data of plaintext or cipertext, which brings lower clock cycles and increased working frequencies. Pipelining architecture inside the round function also contributed a lot to the promotion of data throughput. Moreover, the key schedule algorithm is pipelined to get the speedup, and the S-boxes which are based on look-up tables (LUTs) could be area-efficient. By conducting ALTERA FPGA realization and ModelSim simulation, we analyze the performance relating to the Slice registers, gate-level netlists, memory, Slice LUTs and so on.
Keywords :
clocks; cryptography; field programmable gate arrays; parallel architectures; pipeline processing; power aware computing; table lookup; AES; ALTERA FPGA realization; DES; ModelSim simulation; S-boxes; Slice LUT; Slice registers; celerity hardware implementation; cipertext data; clock cycles; data encryption standard; data parallel architecture; data pipelining architecture; gate-level netlists; hardware applications; look-up tables; plaintext data; round function; security-constrained applications; software applications; Clocks; Encryption; Hardware; Pipeline processing; Registers; Throughput; AES; Data parallel; High-throughput; Round Function Pipelining;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Trust, Security and Privacy in Computing and Communications (TrustCom), 2013 12th IEEE International Conference on
Conference_Location :
Melbourne, VIC
Type :
conf
DOI :
10.1109/TrustCom.2013.210
Filename :
6681036
Link To Document :
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