Title :
Simulator Implementation and Performance Study of a Polymorphous Array Computer
Author :
Hucai Huang ; Tao Li ; Jungang Han
Author_Institution :
Sch. of Comput. Sci., Xi´an Univ. of Posts & Telecommun., Xi´an, China
Abstract :
This paper reports the implementation of a simulation platform and the performance study for the PAAG array processor. PAAG is a novel, polymorphous array architecture that is capable of supporting a dynamic mixture of data parallel computation (DLP), thread level parallel computation (TLP), and instruction level parallel computation (ILP). Simulation experiments have been conducted on the simulation platform and results are reported here. This confirms that PAAG is able to achieve satisfactory performance while running a mixture of data parallel, thread parallel and instruction level program segments.
Keywords :
digital simulation; multi-threading; parallel architectures; DLP; ILP; PAAG array processor; TLP; data parallel computation; instruction level parallel computation; polymorphous array computer; thread level parallel computation; Application specific integrated circuits; Arrays; Message systems; Parallel processing; Pipelines; Routing; Parallel computation; data parallelism; instruction level parallelism; message routing; polymorphous architecture; thread level parallelism; thread scheduling;
Conference_Titel :
Trust, Security and Privacy in Computing and Communications (TrustCom), 2013 12th IEEE International Conference on
Conference_Location :
Melbourne, VIC
DOI :
10.1109/TrustCom.2013.229
