IC Design of a Low-Power Analog LDPC Decoder Employing New Stopping Iteration Method

This paper proposes an analog LDPC decoder employing new stopping iteration method. It is based on the min-sum algorithm and by checking parity H-matrix to decide iteration termination. The proposed method not only can increase the decoding throughput but also decrease the power consumption. Experimental results show that this decoder can save 90% power consumption speed ratio compared with traditional decoders. Finally, an analog (32, 8) min-sum decoder with new stopping iteration method is implemented by TSMC 0.18μm 1P6M CMOS technology. When the data throughput and supply voltage is 216 Mb/s and 1.8V respectively, the power consumption is only 4.98 mW. This analog decoder has low power and small area characteristics that can be applicable to green communication devices.