An Energy Efficient Cache Design for Multi-core Processors

Multi-core processors have become the main development trend of processor, because of their advantages of performance and power dissipation. The multi-core structure leads to many new features for on-chip memory system, such as much larger capacity of cache, more complex circuit for cache sharing management of different threads. The low power issue is still a big deal for multi-core processors, since more and more application environment is power-constrained. To deal with the new challenge of energy efficient cache design for multi-core processors, we extend the low power cache design - "filter cache" which has been widely used in single core processor to the multi-core structure. A public-filter is inserted at level-0 as the first instruction source for all the cores and a dynamic management method is also applied for the public-filter. It can dynamically allocate the public-filter for each core by the runtime filter hit ratio. The experiment results show that the presented method can save about 29% energy and almost has no performance loss.