A Compensated Technique for 2.5-GHz Ring-Oscillator-Based PLL used in Wireless Transmission

A novel topology of PLL based on a new compensated VCO has been proposed in this paper. It is shown that the VCO can compensate supply noise and other factors with an optimum varactor value efficiently, and the on-chip calibration block can find this varactor value automatically. The PLL is fabricated and tested on 0.18-μm CMOS process demonstrates robust performance against the supply variation. The measured rms jitter of the proposed PLL with on-chip calibration is 3ps at 2.5GHz operation frequency. The total power consumption of the PLL with the calibration block is 27mW.