Mixed Mode Circuit Simulation of a Junction-Less Transistor and a Comparative Study with CMOS Inverter

Author

Biju, Nitha M. ; Aswathy, M. ; Komaragiri, Rama

Author_Institution

Dept. of ECE, St.Joseph Coll. of Eng. & Technol., Palai, India

fYear

2013

fDate

29-31 Aug. 2013

Firstpage

141

Lastpage

144

Abstract

Dual Gate Enhancement Mode Junction Field Effect Transistor (DG-JFET) are recognized as one of the possible choice to continue the scaling beyond the conventional limits. In this work, from device perspective, characteristics and inverter characteristics of DG-JFETs and Metal Oxide Semiconductor Field Effect Transistors(MOSFETs) are studied using mixed-mode simulations. The circuit simulation results show that enhancement mode DG-JFET inverters offer excellent ON/OFF performance and better noise margin at a power supply voltage of 0.65 V a requirement for ultra low voltage applications.

Keywords

CMOS integrated circuits; MOSFET; circuit simulation; invertors; junction gate field effect transistors; CMOS inverter; DG-JFET; MOSFET; dual gate enhancement mode junction field effect transistor; junction-less transistor; metal oxide semiconductor field effect transistors; mixed mode circuit simulation; ultralow voltage applications; voltage 0.65 V; CMOS integrated circuits; Inverters; JFETs; Logic gates; Noise; Performance evaluation; CMOS SOI; Double Gate; Inverter; JFET; Junction less transistor; Mixed Mode Simulation; Noise Margin; low-power;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing and Communications (ICACC), 2013 Third International Conference on

Conference_Location

Cochin

Type

conf

DOI

10.1109/ICACC.2013.99

Filename

6686356