DocumentCode :
655425
Title :
Design and FPGA Implementation of a Programmable Data Rate PSK Digital Demodulator for Onboard and Ground Applications
Author :
Kumar, Manoj ; Tank, V.K. ; Ram, T.V.S.
Author_Institution :
Space Applic. Centre (SAC), Indian Space Res. Organ. (ISRO), Ahmedabad, India
fYear :
2013
fDate :
29-31 Aug. 2013
Firstpage :
437
Lastpage :
440
Abstract :
In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports variable data rates varying from 4.88Kbps to 2Mbps and higher is described. The paper presents the design of carrier and symbol recovery loops in details. The design is made platform independent so that it can be ported to any FPGA device. Proposed design is targeted for Xilinx Virtex-II pro FPGA xc2vp50-6ff 1152 for Hardware proof of concept. The complete demodulator occupies only 13% of the available logic slices in Xilinx Virtex-II pro FPGA device.
Keywords :
demodulators; field programmable gate arrays; logic design; on-board communications; phase shift keying; satellite communication; FPGA implementation; Xilinx Virtex-II pro FPGA device; carrier recovery loop; hardware proof; logic slices; programmable data rate PSK digital demodulator; symbol recovery loop; Demodulation; Field programmable gate arrays; Finite impulse response filters; Hardware; Matched filters; Phase shift keying; Tracking loops; BER; CIC; Digital Demodulation; Eb/No; FPGA; Phase Shift Keying; Programmable Bandwidth;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advances in Computing and Communications (ICACC), 2013 Third International Conference on
Conference_Location :
Cochin
Type :
conf
DOI :
10.1109/ICACC.2013.93
Filename :
6686425
Link To Document :
بازگشت