A parameter identification algorithm for multi-stage digital predistorter

In this paper, we propose an algorithm to identify the parameters of a multi-stage digital predistorter (PD). In multi-stage PD, digital predistortion (DPD) is implemented in two or more stages. Using the proposed algorithm each stage of the multi-stage PD can be identified separately by taking into account the contribution of all other stages. The algorithm is iterative and shown to converge after few system-level iterations. Through system level simulation, it has also been demonstrated that the proposed algorithm can be successfully used to identify the parameters of two-box, three-box or multi-stage memory polynomial (MP) predistorters. The performance of the proposed algorithm is evaluated by measuring the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) at the output of power amplifier (PA) when a Long Term Evolution-Advanced (LTE-Advanced) signal is applied at the input.