Title :
Novel millimeter-wave PLL synthesizer with cascaded phase detectors
Author :
Matsumura, Hiroshi ; Kawano, Yoshihiro ; Sato, Mitsuhisa ; Ohshima, T. ; Shimura, Toshihiro ; Suzuki, Takumi ; Ohashi, Yoshimasa ; Hara, Naoya
Author_Institution :
Fujitsu Ltd., Kanagawa, Japan
Abstract :
We present a novel millimeter-wave PLL architecture with cascaded phase detectors. It exhibits low phase noise and low spurious characteristics concurrently. The 79-GHz band PLL synthesizer was developed in 65-nm CMOS technology. It achieves a phase noise of -90.0 dBc/Hz at 1 MHz offset and a normalized phase noise of -231.2 dBc/Hz2 at 1 MHz offset using a 49-MHz on-chip reference oscillator. The PLL exhibits low-level reference spurs of -29.3 dBc at 49 MHz and -36.0 dBc at 98 MHz.
Keywords :
CMOS integrated circuits; millimetre wave integrated circuits; phase detectors; phase locked loops; phase noise; CMOS technology; cascaded phase detector; frequency 1 MHz; frequency 49 MHz; frequency 79 GHz; frequency 98 MHz; millimeter-wave PLL synthesizer; on-chip reference oscillator; phase noise; size 65 nm; spurious characteristic; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; Phase locked loops; Time-frequency analysis; Voltage-controlled oscillators; CMOS integrated circuits; Millimeter-wave integrated circuits; Phase detection; Phase locked loops; Phase noise;
Conference_Titel :
Microwave Integrated Circuits Conference (EuMIC), 2013 European
Conference_Location :
Nuremberg
