Title :
New Beta-Matrix topology in CMOS32nm and beyond for ESD/LU improvement
Author :
Bourgeat, Johan ; Jimenez, Joaquin ; Dudit, Sylvain ; Galy, Ph
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
This paper is focused on the optimization of Beta-Matrix power device to protect thin oxide GO1 =1 V and thick oxide G02=1.8V. The study investigates Beta-Matrix topology and particularly the impact of elementary pattern on device behavior. This work is mainly carried on 3D TCAD simulations. The best configurations, with lower voltage triggering have been realized in CMOS32nm high k metal gate and characterized thanks Transmission Line Pulse (TLP) with 100ns width.
Keywords :
CMOS analogue integrated circuits; high-k dielectric thin films; technology CAD (electronics); 3D TCAD simulation; CMOS high-k metal gate; ESD-LU improvement; beta-matrix power device optimization; beta-matrix topology; elementary pattern impact; size 32 nm; time 100 ns; transmission line pulse; voltage 1 V; voltage 1.8 V; voltage triggering; Electrostatic discharges; Logic gates; Optimization; Robustness; Thyristors; Topology; Trigger circuits; Beta-Matrix; ESD; Network; elementary pattern;
Conference_Titel :
Semiconductor Conference (CAS), 2013 International
Conference_Location :
Sinaia
Print_ISBN :
978-1-4673-5670-1
Electronic_ISBN :
1545-827X
DOI :
10.1109/SMICND.2013.6688644
