ESD protection with BIMOS transistor for bulk & FDSOI advanced CMOS technology

The purpose of this paper is to introduce the ESD protection using BIMOS transistor in bulk CMOS and in hybrid area for 28nm FDSOI High k metal gate. Moreover the DC behavior is also performed. Thus, this study introduces an ESD protection with a minimum of silicon area consumption and efficient to protect the MOS transistors with thin & thick oxide and also in thin silicon film. TCAD simulations are done in 2D and 3D with classical equation of semiconductor. Moreover, all results are done through silicon measurements on demonstrator devices.