Analytical performance analysis of mesh network-on-chip based on network calculus

The design of on chip interconnection architecture (NoC) should carefully take on consideration both hardware and communication constraints in order to built up a system that meets quality of service requirements. In NoC architecture, the on chip switch available hardware and software resources drive up the global performances of communication processes. Therefore it is crucial, before the physical design process, to carry out the required capacities such as buffer depth and management-tasks of a flit. In fact, one of the most critical parameters that can affect communication characteristics are the available memory space in addition to flit-time processing according to a given scheduling approach. This paper deals with these concepts. It presents a study of NoC switch using Network Calculs (NC) theory. It provides an analytic model of the internal on chip switch architecture to study the performance with a mathematical approach. This helps to specify the best physical and logical characteristics that can achieve enhanced performances.