Interface State Density of Single Vertical Nanowire MOS Capacitors

An investigation of trap states at the semiconductor-oxide interface of single silicon nanowires is presented using vertical gate-all-around nanowire MOS capacitors. By performing highly accurate capacitance-voltage measurements at room temperature, the energetic distribution of interface traps D_it could be extracted with the quasi-static method. Although the capacitance of a single nanowire MOS capacitor with Al₂O₃ gate oxide is only 2 fF, D_it values were obtained with good reproducibility. For etched, vertical Si nanowires, D_it in the range of (4 ±1) × 10¹² cm^-2eV^-1 was obtained.