A Frequency Agile, Self-Adaptive Serial Link on Xilinx FPGAs

Author

Aloisio, A. ; Giordano, R. ; Izzo, V. ; Perrella, S.

Author_Institution

Univ. di Napoli “Federico II”, Naples, Italy

Volume

62

Issue

3

fYear

2015

fDate

Jun-15

Firstpage

955

Lastpage

962

Abstract

In this paper, we focused on the GTX transceiver modules of Xilinx Kintex 7 field-programmable gate arrays (FPGAs), which provide high bandwidth, low jitter on the recovered clock, and an equalization system on the transmitter and the receiver. We present a frequency agile, auto-adaptive serial link. The link is able to take care of the reconfiguration of the GTX parameters in order to fully benefit from the available link bandwidth, by setting the highest line rate. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to control the quality of the received data and to easily calculate the bit-error rate in each sampling point of the eye diagram. We present the self-adaptive link project, the description of the test system, and the main results.

Keywords

field programmable gate arrays; jitter; microcomputers; transceivers; FPGA-embedded microprocessor; GTX transceiver modules; Xilinx FPGA; Xilinx Kintex 7 field-programmable gate arrays; autoadaptive serial link; bit-error rate; equalization system; eye diagram; jitter; receiver; recovered clock; self-adaptive link project; self-adaptive serial link; transmitter; Bit error rate; Clocks; Equalizers; Field programmable gate arrays; Random access memory; Receivers; Transceivers; Bit-error rate (BER); field-programmable gate array (FPGA); serial links; transceivers;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2015.2423674

Filename

7108076