Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise

As technology further scales, inaccurate prediction of IR-drop effect during scan testing could cause significant under estimation of the critical path delay, and further leads to serious issues such as insufficient guard band application, test escape, chip mis-binning and more. In this paper, a novel layout-aware path delay test generation method is proposed to maximize the effect of power-supply noise on target paths during delay test. It is able to estimate supply noise fast by calculating transition propagation probability and running fault simulation. Based on such estimation, the correlation between path-delay fault (PDF) and transition-delay fault (TDF) patterns is calculated to find the best sequence to merge patterns. The final generated path-delay test is able to simultaneously increase the local and global power-supply noise, thus furthur capture the worst-case timing scenarios of the target path. Experimental results show that the final PDF pattern can increase the path delay significantly comparing with the nominal PDF pattern and the best randomly-filled PDF pattern.