A New March Test for Process-Variation Induced Delay Faults in SRAMs

Process variations are growing with technology scaling towards nano-scale. This brings new challenges to the design of memory modules, which are often the first circuits to be fabricated using a new technology and usually designed with critical timing. We observed that several delay faults, which are dependent on address transitions, may escape traditional march tests. This paper presents a new march test WT that targets such delay faults. Through Monte Carlo simulations and analytical studies on SRAM designs using an industrial 65nm process, we have demonstrated that WT provides a faulty-chip-coverage that is close to 100%. Most importantly, this is the first march test with test length that targets address-dependent delay faults and hence the first delay test which can be used in practice.