Title :
Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects
Author :
Chao Han ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
Hazards have been known to have the potential to invalidate tests for stuck-open faults in CMOS circuits. In this paper we show that hazards can also predictably allow the detection of stuck-open faults that may be undetectable by traditional TDF launch-on-capture (LOC) scan delay tests. Importantly, the detected open faults are not redundant, and can in fact be activated in normal functional operation leading to functional errors. We identify such defects in benchmark circuits and present a LOC test selection method capable of predictably detecting the open defects through initialization by a hazard.
Keywords :
CMOS integrated circuits; fault diagnosis; integrated circuit testing; logic testing; CMOS circuits; CMOS open defects; TDF undetectable; benchmark circuits; launch-on-capture scan delay tests; stuck-open faults; Automatic test pattern generation; Circuit faults; Delays; Hazards; Logic gates; Transistors; CMOS; LOC; TDF; hazards; stuck-open;
Conference_Titel :
Test Symposium (ATS), 2013 22nd Asian
Conference_Location :
Jiaosi Township
DOI :
10.1109/ATS.2013.43