Testing Disturbance Faults in Various NAND Flash Memories

Author

Chih-Sheng Hou ; Jin-Fu Li

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2013

fDate

18-21 Nov. 2013

Firstpage

221

Lastpage

226

Abstract

NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot, some NAND flash memories with single-page word lines and some with multiple-page word lines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

Keywords

NAND circuits; flash memories; logic testing; random-access storage; NAND flash memories; disturbance faults; nonvolatile memory; Arrays; Ash; Circuit faults; Flash memories; Organizations; Random access memory; Testing; NAND flash; disturbance faults; testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ATS), 2013 22nd Asian

Conference_Location

Jiaosi Township

ISSN

1081-7735

Type

conf

DOI

10.1109/ATS.2013.49

Filename

6690645