Title :
A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications
Author :
Krishnaswamy, Venkatesh ; Shin, Jinuk Luke ; Turullols, Sebastian ; Hart, John M. ; Konstadinidis, G. ; Huang, Dijiang
Author_Institution :
Oracle, Santa Clara, CA, USA
Abstract :
The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.
Keywords :
cache storage; microprocessor chips; peripheral interfaces; processor scheduling; BL8 DDR3-1066 schedulers; SPARC S3 cores; SPARC T4 CPU; SPARC T5 processor; integrated PCIe Gen-3; metal stack; set-associative L3 cache; single hop glueless fashion; socket systems; transistors; Bandwidth; Clocks; Coherence; Frequency locked loops; Metals; Sockets; Timing;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6690971
