Title :
A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS
Author :
Yan Zhu ; Chi-Hang Chan ; Seng-Pan, U. ; Martins, Rui P.
Author_Institution :
State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China
Abstract :
This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; flip-flops; CMOS; DAC linearity calibration; SAR ADC; bridge DAC structure; conversion nonlinearity; digital circuitry; digital domain; phase-splitting bit register; power 3.2 mW; size 90 nm; voltage 1.2 V; Arrays; Calibration; Capacitors; Linearity; Parasitic capacitance; Registers;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6690984
