A 12b 1.7GS/s two-times interleaved DAC with <-62dBc IM3 across Nyquist using a single 1.2V supply

A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit´s active area is 0.4mm² and the power consumption is 70mW from a nominal 1.2V supply.