750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder

Author

Abolfazli, Alireza Rabbani ; Shayan, Yousef R. ; Cowan, Glenn E. R.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada

fYear

2013

fDate

11-13 Nov. 2013

Firstpage

181

Lastpage

184

Abstract

Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes implemented to date using analog techniques. At a Bit Error Rate of 10^-5, the measured performance is within 0.2dB of modeled performance using floating-point arithmetic. The chip was tested at a throughput of 750Mb/s. This improves the throughput of analog decoders by a factor of 57. The power dissipation of the core is 13 mW resulting in 17pJ/b energy efficiency. The core area is 1.38mm². The fabricated MS-based TS-LDPC analog decoder has BER performance nearly identical to theory without compromising energy efficiency.

Keywords

CMOS integrated circuits; codecs; error statistics; floating point arithmetic; integrated circuit testing; parity check codes; turbo codes; BER performance; CMOS technology; IC implementation; MS-based TS-LDPC analog decoder; analog techniques; bit error rate; bit rate 750 Mbit/s; chip testing; energy efficiency; floating-point arithmetic; min-sum based turbo-structured LDPC analog decoder; power 13 mW; power dissipation; size 90 nm; Bit error rate; CMOS integrated circuits; Decoding; Parity check codes; Reactive power; Semiconductor device measurement; Throughput; Analog VLSI; Decoder; LDPC code;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian

Conference_Location

Singapore

Print_ISBN

978-1-4799-0277-4

Type

conf

DOI

10.1109/ASSCC.2013.6691012

Filename

6691012