A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

Author

Umeki, Yohei ; Yanagida, Koji ; Yoshimoto, Shusuke ; Izumi, Shintaro ; Yoshimoto, Masahiko ; Kawaguchi, Hitoshi ; Tsunoda, Koji ; Sugii, Toshihiro

Author_Institution

Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan

fYear

2013

fDate

11-13 Nov. 2013

Firstpage

249

Lastpage

252

Abstract

This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.

Keywords

MRAM devices; STT-MRAM; boosted-gate nMOS; frequency 0.526 MHz; negative-resistance pMOS; power 6.15 muW; process variation tolerant sense amplifier; size 65 nm; spin transfer torque magnetoresistance random access memory; time 1.9 mus; voltage 0.38 V; voltage 0.44 V; Bandwidth; Charge pumps; IP networks; Logic gates; Magnetic tunneling; Random access memory; Transistors; Low voltage; Process variation tolerant; STT-MRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian

Conference_Location

Singapore

Print_ISBN

978-1-4799-0277-4

Type

conf

DOI

10.1109/ASSCC.2013.6691029

Filename

6691029