Title :
A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS
Author :
Hung-Yen Tai ; Pao-Yang Tsai ; Cheng-Hsueh Tsai ; Hsin-Shu Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 6-bit 1.25GS/s single-channel asynchronous SAR ADC skipping the comparator metastability is presented. A delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range and to accelerate the comparison speed. It compensates the dynamic offset by the redundancy. This ADC in 40nm CMOS technology achieves 37.1dB peak SNDR and consumes 5.3mW at 1.2V supply. It results in an FoM of 73fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.004mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; comparators (circuits); integrated circuit reliability; CMOS integrated circuit; asynchronous SAR ADC; comparator delay; comparator metastability; delay shift technique; dynamic offset compensation; power 5.3 mW; redundancy rate; single channel SAR ADC; size 40 nm; successive approximation register; voltage 1.2 V; CMOS integrated circuits; Calibration; Capacitors; Redundancy; Semiconductor device measurement; Solid state circuits; Switches; Analog to digital converter (ADC); metastability; redundancy; successive approximation register (SAR);
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691036
