Title :
A 3x blind ADC-based CDR
Author :
Jalali, Mohammad Sadegh ; Ting, Chih-Hung ; Abiri, Behrooz ; Sheikholeslami, Ali ; Kibune, Masaya ; Tamura, H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu\´s 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16" FR4 channel.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clock and data recovery circuits; jitter; power consumption; ADC resolution; CMOS; baud rate; blind ADC-based CDR; high frequency jitter tolerance; power consumption; Accuracy; Clocks; Decision feedback equalizers; Frequency measurement; Interpolation; Power demand; Semiconductor device measurement;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691054
