Title :
A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology
Author :
Xiang Yi ; Chirn Chye Boon ; Junyi Sun ; Nan Huang ; Wei Meng Lim
Author_Institution :
Sch. of Electr. Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
A low phase noise 24/77 GHz dual-band subsampling PLL with a dual-band VCO is presented. Implemented in 65 nm CMOS technology, the proposed PLL occupies an area of 900 μm × 550 μm. The measured phase noise is -120.0 and -108.5 dBc/Hz at 1 MHz offset in 24 and 77 GHz modes respectively. With 1.3 V supply, the power consumption is 26.4 and 31.5 mW for 24 and 77 GHz modes respectively. Compared with other state-of-the-art works, the proposed PLL has the best phase noise performance among all of reported PLLs for automotive radar applications.
Keywords :
CMOS integrated circuits; phase locked loops; phase noise; road vehicle radar; voltage-controlled oscillators; CMOS technology; automotive radar applications; dual-band VCO; dual-band sub-sampling PLL; frequency 24 GHz; frequency 77 GHz; phase noise; power 26.4 mW; power 31.5 mW; size 550 mum; size 65 nm; size 900 mum; voltage 1.3 V; Automotive engineering; CMOS integrated circuits; Dual band; Phase locked loops; Phase noise; Radar; Voltage-controlled oscillators; 24 GHz; 77 GHz; CMOS; Phase-locked loop (PLL); automotive radar; dual-band; low phase noise; sub-sampling; voltage-controlled oscillator (VCO);
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-0277-4
DOI :
10.1109/ASSCC.2013.6691071
