A new efficient layer assignment algorithm for partitioning in 3D VLSI physical design

Partitioning is a key problem in VLS I physical design. In partitioning, the circuit is partitioned into subcircuits. These sub-partitions are called blocks. In 3D partitioning, each of these blocks is assigned into one layer. Our primary goal is to minimize the interconnection between non-adjacent layers so that the wire length can be minimized. This process is called layer assignment. In this paper, first we propose a new efficient technique using adjacency matrix of a graph for layer-assignment problem. Next, we show the technique using an example. After that the implementation result is shown, and conclude the paper.