Title :
A balanced High Voltage IGBT design with ultra dynamic ruggedness and area-efficient edge termination
Author :
Ze Chen ; Nakamura, Katsumi ; Nishii, Akito ; Terashima, Tomohide ; Kawakami, Tsuyoshi
Author_Institution :
Power Semicond. Device Dev. Dept., Mitsubishi Electr. Corp., Fukuoka, Japan
Abstract :
In this paper, a balanced High Voltage (HV) IGBT is presented. The proposed HV IGBT is composed of three technologies: Wide Cell Pitch CSTBTTM(III) for cell structure, Partial P collector utilizing LPT(II) buffer for vertical structure, and a novel area-efficient edge termination design. We called the above edge termination design “Linearly-narrowed Field Limiting Ring (LNFLR)”. The experiment results of a balanced 4500 V class IGBT show that the device maintains an excellent dynamic ruggedness with a 50% cut in edge termination width comparing to the conventional Field Limiting Ring (FLR) design. Moreover, optimizing fabrication process can further widen the process window for LNFLR dose.
Keywords :
insulated gate bipolar transistors; power bipolar transistors; LNFLR; LPT(II) buffer; area efficient edge termination design; balanced high voltage IGBT design; carrier stored trench bipolar transistor; light punch through buffer; linearly-narrowed field limiting ring; partial P collector; process window; ultra dynamic ruggedness; voltage 4500 V; wide cell pitch CSTBTTM(III); Current density; Electric fields; Fabrication; Insulated gate bipolar transistors; Junctions; Switches; Voltage measurement;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4673-5134-8
DOI :
10.1109/ISPSD.2013.6694393