Title :
Current balancing control for parallel connected IGBTs using programmable gate driver output resistance
Author :
Sasaki, M. ; Nishio, H. ; Shorten, A. ; Ng, W.T.
Author_Institution :
Power Semicond. Dev. Div., Fuji Electr. Co., Ltd., Matsumoto, Japan
Abstract :
A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Rout to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Rout is implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMC´s 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.
Keywords :
BIMOS integrated circuits; current distribution; delays; driver circuits; electric current control; insulated gate bipolar transistors; integrated circuit design; integrated circuit manufacture; integrated circuit technology; programmable circuits; IC fabrication; TSMC BCD Gen-2 process; current 90 A; current balancing control; current distribution measurement; parallel connected IGBT; programmable gate driver IC design; programmable gate driver output resistance; segmented output stage technique; size 0.18 mum; turn-on-off delay time; voltage 600 V; Delays; Insulated gate bipolar transistors; Integrated circuits; Logic gates; Resistance; Switches;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4673-5134-8
DOI :
10.1109/ISPSD.2013.6694398
