Current balancing control for parallel connected IGBTs using programmable gate driver output resistance

Author

Sasaki, M. ; Nishio, H. ; Shorten, A. ; Ng, W.T.

Author_Institution

Power Semicond. Dev. Div., Fuji Electr. Co., Ltd., Matsumoto, Japan

fYear

2013

fDate

26-30 May 2013

Firstpage

65

Lastpage

68

Abstract

A gate driver IC with programmable output resistance (R_out) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver R_out to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver R_out is implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMC´s 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.

Keywords

BIMOS integrated circuits; current distribution; delays; driver circuits; electric current control; insulated gate bipolar transistors; integrated circuit design; integrated circuit manufacture; integrated circuit technology; programmable circuits; IC fabrication; TSMC BCD Gen-2 process; current 90 A; current balancing control; current distribution measurement; parallel connected IGBT; programmable gate driver IC design; programmable gate driver output resistance; segmented output stage technique; size 0.18 mum; turn-on-off delay time; voltage 600 V; Delays; Insulated gate bipolar transistors; Integrated circuits; Logic gates; Resistance; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on

Conference_Location

Kanazawa

ISSN

1943-653X

Print_ISBN

978-1-4673-5134-8

Type

conf

DOI

10.1109/ISPSD.2013.6694398

Filename

6694398