DocumentCode
661540
Title
True 3D packaging solution for stacked vertical power devices
Author
Rouger, N. ; Benaissa, L. ; Widiez, J. ; Imbert, B. ; Gaude, V. ; Verrun, S. ; Crebier, J.C.
Author_Institution
G2Elab, Univ. Grenoble Alpes, Grenoble, France
fYear
2013
fDate
26-30 May 2013
Firstpage
97
Lastpage
100
Abstract
This paper presents recent advances and breakthroughs of an alternative 3D packaging solution for vertical power devices. Direct bonding technology and trench isolation used for power device islanding are the cornerstone of this scheme of integration. Involving direct copper bonding layers, the technology is used during the mid-process to enable the wafer level bonding of vertical power devices to a joint metallic substrate while optimizing the devices intrinsic performances. Wafer level islanding and interconnect is used to simplify and guarantee the true 3D assembly at module level. This 3D assembly is based on the interconnect of matrices of low side and high side vertical power devices on top of each other. Our technology optimizes component surface height as well as alignments constraints. As a result, the true 3D integration of the active parts for power converters is optimized to the highest possible level, leading to strongly reduced EMI levels and increased switching speed capabilities. Key challenges, both on design, fabrication and implementation are presented, and the first prototypes based on four switching cells of vertical 500V power diodes and MOSFETs are introduced.
Keywords
integrated circuit interconnections; isolation technology; power MOSFET; power convertors; semiconductor diodes; wafer bonding; wafer level packaging; 3D assembly; 3D packaging solution; MOSFET; alignments constraints optimisation; component surface height optimisation; devices intrinsic performances; direct copper bonding layers; joint metallic substrate; module level; power converters; power device islanding; stacked vertical power devices; switching cells; switching speed capabilities; trench isolation; true 3D integration; vertical power diodes; voltage 500 V; wafer level bonding; wafer level islanding; Assembly; Bonding; Copper; Power transistors; Silicon; Substrates; Three-dimensional displays; Power device assembly; direct bonding technology; electrical characterization; multiple device module;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location
Kanazawa
ISSN
1943-653X
Print_ISBN
978-1-4673-5134-8
Type
conf
DOI
10.1109/ISPSD.2013.6694405
Filename
6694405
Link To Document